I am planning to use modbus protocol for communication in my system, but my master controller is FPGA. I have searched on net that if anyone have done it before but most of them have done it using some processor core. I just want to have an opinion that if it is possible to implement it without using any processor or controller core.

 

I am pretty sure, it is possible. But I am not very sure how you would go about it and how much time it would take. All protocols need libraries and function calls and the likes. In FPGAs you would have to build your own libraries and then call them from your source.

I think you should read some implementation notes on Modbus.org to see if they have existing libraries used for FPGAs and Micros etc. I did a DNP3 algorithm based on MFC class and that was a tough cookie. I am sure implementing Modbus on a FPGA or the likes would be a very time consuming ordeal.

 

hello,

is it possible to use FPGA as master for Modbus protocol? if you have done it can you plz give the details of it. am also confused with Master/slave configuration using FPGA.

 

> is it possible to use FPGA as master for Modbus protocol?

The short answer is Yes - It is possible.

But I would do it using a processor soft core. Xilinx has the MicroBlaze 8-bit core which I have used to implement deep FIFO serial ports. They also have more advanced cores but it sounds like you wish to keep it simple?

What FPGA and hardware are you targeting?

 

Thank you for the reply..

am having sparten 3 and vertex II pro. how to configure slaves if i consider fpga as master? and using vhdl What shld i do for 3.5c idle bits..

 

> am having sparten 3 and vertex II pro. how to configure slaves if i consider
> fpga as master? and using vhdl What shld i do for 3.5c idle bits..

Are you also designing the slaves?

The slaves will need an unique slave address for each slave, all the same baud rate, parity and stop bits and all the same mode (RTU sounds like the mode you are going to use).

As for the master design the FPGA hardware would need to be defined (I use Xilinx's XPS). In this case define UART port and I would use two timers (one for the character to character inter-frame t1.5 and one for the frame to frame intra-frame t3.5). The timers can be setup to interrupt as well as the UART on received characters.

jim b